The invention relates to a method and apparatus for maintaining the phase relationship between a computer's clock signals and associated data, and, more specifically, to a phase delay compensator circuit which compensates for the phase error caused by propagation delay differences between clock and data signal paths.
The design of modern high performance computer systems typically involves development of individual subsystems or sub-assemblies, examples of which include a central processing unit, a memory unit, system clock unit, a system control unit, and an input/output (I/O) unit. These sub-assemblies, which are thereafter integrated to form the computer system, may be physically separated from one another, thereby requiring transmission lines or cables to connect the sub-assemblies and provide a means for transfering or communicating information between them. If the distance between the sub-assemblies change, then different length cables are required.
The system clock unit typically creates clock signals used for timing the computer's electronic components and devices. In a frequency-agile synchronous computer system, the frequency of the system clock may dynamically change due to diagnostic testing, that is, the frequency of the created clock signals may be altered as part of the diagnostic testing without having to power-down the computer system. These clock signals are then distributed along cables to the other sub-assemblies within the computer system.
When communicating between different sub-assemblies, it is desirable for the clock signals and its associated data to arrive at a destination, such as a state device or flip-flop, in a defined manner to ensure proper computer operation. In other words, the position of the clock signal used for enabling the state device relative to the data to be stored by that device must be maintained in a defined timing relationship to avoid a race condition. In many circuits or logic networks, a situation may occur where more than one state device in the network must change state, or its stored value, in response to a single change in the network's input. A race condition arises when the possibility exists that one of two different stable states may result depending upon the order in which the devices change state.
In order to avoid a race condition and maintain a defined sequence of device operation within the computer system, it is desirable that the cables or paths along which the clock and data signals propagate have approximately equal propagation delay characteristics. Propagation delay is the time needed by a signal to travel from a transmitter to a receiver. Tolerance variations in the manufacture of similar components such as cables may introduce unpredictable skewing in the transmission of signals, that is, the variations may introduce additional delay differences between the clock and data paths. Also, changing the length of the cables used to connect the sub-assemblies could add delay into the signal paths. The occurance of such physical events may potentially alter the phase or timing relationship between the clock and data signals. On the other hand, a changing of frequency of the system clock, referred to as a system designed event, may vary the position of the distributed clock signals relative to the data and require signal phase adjustment to compensate for any resulting phase or timing error.
Attempts to adjust the phase of clock signals typically involved a circuit that created multiple phases of a particular reference clock signal, the reference clock signal being loaded into a shift register by a master clock signal. The output of the shift register was then presented to a selector where phase selection was performed. However, the use of commercially available electronic components to implement the selecting logic function introduced additional skew in the circuit path, causing significant delay and constraining performance of the overall circuit.
Therefore, in accordance with an aspect of the present invention, a feature is to provide a phase delay compensator circuit which minimizes the logic required for clock phase selection in order to increase clocking speed.
Additionally, a feature of the present invention is to provide a phase delay compensator which allows the changing of cables connecting various sub-assemblies of a computer system without causing timing race conditions.
In accordance with another aspect of the invention, a feature is to provide a phase delay compensator which compensates for the phase error caused by propagation clock signal to data path differences.
A further feature of the present invention is to provide a phase delay compensator which allows the changing of the frequency of a synchronous computer's system clock without causing timing race conditions.